标准摘要
[中文适用范围]： 本标准聚焦于集成电路设计的延迟和功耗计算，支持逻辑行为和信号完整性的建模。 [外文原描述]： IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity. The standard specifications covered in this document are as follows: - Description language for timing and power modeling, called the “delay calculation language” (DCL) - Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions - Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF) - Informative usage examples - Informative notes. This is an IEC/IEEE dual logo standard.
英文名称Delay and power calculation standards - Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)