标准摘要
[中文适用范围]： 适用于 CMOS ASIC 库，其中包含要在逻辑仿真、时序验证和逻辑综合的预布局设计阶段使用的基于单元的原语和存储器。本标准中涉及的延迟计算方法包括： [外文原描述]： Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.
英文名称Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries