标准摘要
[中文适用范围]： 提供用 VHDL 建模 ASIC 的标准方法。该方法旨在提供高效、准确且独立于工具的仿真，适用于典型的基于 ASIC 的大型芯片级设计。该出版物的状态为 [外文原描述]： Providse a standard method of modeling ASICs in VHDL.This method is aimed at providing efficient, accurate,and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs. This publication has the status of a double logo IEEE/IEC standard
英文名称Behavioural languages - Part 5: VITAL ASIC (application specific integrated circuit) modeling specification