标准摘要
[中文适用范围]： 指定使用超高速集成电路硬件描述语言 (VHDL) 来建模可综合寄存器传输级数字逻辑的标准。定义了 VHDL 寄存器传输级综合的标准语法和语义。时间 [外文原描述]： Specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.
英文名称VHDL Register Transfer Level (RTL) synthesis