半导体压模产品.第5部分:关于电子模拟的信息要求

[中文适用范围]： IEC 62258 的这一部分旨在促进半导体芯片产品的生产、供应和使用，包括： – 晶圆； – 分割裸芯片； – 带有连接结构的芯片和晶圆； – 最低限度或部分封装的芯片和晶圆。 IEC 62258 的这一部分规定了促进使用电气数据和模型所需的信息，以模拟电气行为并验证电子系统的正确功能，这些电子系统包括裸半导体芯片（带或不带连接结构）和/或最小封装半导体芯片。它旨在帮助芯片器件供应链中的所有参与者遵守 IEC 62258-1 和 IEC 62258-2 的要求。 [外文原描述]： IEC 62258-5:2006 has been developed to facilitate the production, supply and use of semiconductor die products, including: - wafers; - singulated bare die; - die and wafers with attached connection structures; - minimally or partially encapsulated die and wafers. This part of IEC 62258 specifies the information required to facilitate the use of electrical data and models for simulation of the electrical behaviour and verification of the correct functionality of electronic systems that include bare semiconductor die, with or without connection structures, and/or minimally packaged semiconductor die. It is intended to assist all those involved in the supply chain for die devices to comply with the requirements of IEC 62258-1 and IEC 62258-2. This publication is to be read in conjunction with IEC 62258-1:2009 and IEC 62258-2:2011 .