系统级硬件描述语言. 统一硬件设计, 规范和鉴定语言

[中文适用范围]： 本标准提供了IEEE 1800™ SystemVerilog语言的语言语法和语义定义，这是一种统一的硬件设计、规范和验证语言。标准包括对行为、寄存器传输级（RTL）和门级硬件描述的支持；测试平台、覆盖、断言、面向对象和约束随机构造；以及提供对外部编程语言的应用程序编程接口（API）。 [外文原描述]： IEC 62530:2021(E) provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages. This edition corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions. This publication has the status of a double logo IEEE/IEC standard.