多核软硬件接口

[中文适用范围]： 本标准的范围包括复杂处理器（如超长指令字（VLIW）核心）的性能估计准确性，以及复杂争用场景的描述，包括未缓存内存区域和内存子集缓存的描述，粗略功耗估计的属性，以及通过分离可扩展标记语言（XML）文件实现处理器描述和其他内存/通信相关信息的可重用性。 [外文原描述]： IEC 63504-2804:2023 defines an architecture description standard from the software design perspective - this provides a common interface that abstracts the hardware properties that are critical to enable multicore tools. The standard includes performance estimation accuracy for complex processors like Very Long Instruction Word (VLIW) core and complex contention scenarios, description of caches to include uncached memory regions and caches for subsets of memories, properties for coarse power consumption estimation, and reusability by separating eXtensible Markup Language (XML) files for processor description and other memory/communication-related information. This is an IEC/IEEE dual logo standard.