标准摘要
[中文适用范围]： 指定构成多段总线体系结构的一组信号线的逻辑层，以及连接到总线段的模块的接口。 旨在用作配置文件中的组件，以构建具有更高兼容性级别的系统。 [外文原描述]： Specifies the logical layer for a set of signal lines that constitute a multiple segment bus architecture, and for the interfacing of modules connected to a bus segment. Intended to be used as a component within a profile to build systems with higher levels of compatibility.
英文名称Information technology - Microprocessor systems - Futurebus+ - Logical protocol specification